A novel ALU operation technique for parity-preserving gates driven by Xilinx and Verilog HDL
Eswar Rao, V. Santosh Kumar, G. Srikanth, K. Navya · 2025
Due to device scaling brought about by MOSFET invention in1960s, the semiconductor industry has witnessed enormous gains in speed and device performance; yet, power dissipation is also a major problem. As the growth of gadgets reaches a limit, authors are searching for a technology that will change the game. One of the hot areas in VLSI sector right now is reversible computing. Researchers have been primarily interested in this technique because of its negligible power dissipation. An ALU with reversible quantum gates is proposed to be researched in this paper. The proposed ALU can be used for either logical or arithmetic operations, and based on circumstances; it can also identify a single bit error. The parity-preserving Fredkin and CNOT gates are used in the design. Verilog HDL is used to model the suggested design, and Xilinx software is used to excite it. Reducing the number of gates, garbage outputs, quantum costs, and auxiliary or constant inputs is the main goal of the design.