High-Performance Address Translation for Solid-State Drives via Asymmetry Decomposition
Yu-Ta Liu, Shuo-Han Chen · 2025
In the post-AI era, the growing complexity of computer systems has increased the demand for energy-efficient, high-performance storage solutions. Solid-state drives (SSDs), widely used in various applications, face performance bottlenecks in address translation under intensive workloads due to their serial processing architecture. Additionally, under intensive random or parallel I/O workloads, the address translation process in SSDs has emerged as one of the primary bottlenecks due to its serial processing architecture. As NAND flash access latencies decrease with enhanced parallelism, the impact of address translation overhead becomes more pronounced. Although it is possible to accelerate address translation in SSDs by utilizing more processing cores or increasing processing frequency, this performance improvement typically comes at the cost of energy efficiency. Moreover, since the sub-tasks involved in address translation are inherently asymmetric, decomposing the address translation procedure with a symmetric assumption can lead to inefficiencies or contention due to dependencies. These observations motivate the proposal of an asymmetric multiprocessing address translation (AMP-AT) strategy that decomposes address translation into asymmetric sub-tasks and pipelines them to improve performance and energy efficiency. Our approach leverages the inherent asymmetry of sub-tasks to minimize contention and dependencies, achieving significant gains in both metrics, as validated by experimental results.