Efficient Hardware Acceleration of Polar Decoding Using in-Memory Computing for Wireless Communication Systems
Mojtaba Mahdavi · 2025
Polar codes have emerged as a powerful error correction coding scheme, offering capacity-achieving performance in modern communication systems. However, the efficient hardware realization of polar decoding remains a challenge due to its intensive computational requirements. This paper presents a memristor-based in-memory computing (IMC) approach for efficient polar decoding. By reformulating decoding as matrixvector multiplications, computations are directly mapped onto arrays of memristors, minimizing data movement and enabling parallel execution. Leveraging Ohm's and Kirchhoff's laws, the proposed architecture significantly reduces latency and energy consumption. A step-by-step realization of polar decoding within the IMC framework is detailed, demonstrating its scalability and efficiency for next-generation communication systems, paving the way for efficient implementation of advanced coding schemes.