On-chip Acceleration for Log-Structured GDBMS
Alexander Baumstark, Kai-Uwe Sattler · 2025
Emerging memory technologies like HBM or CXL-attached memory provide not only new opportunities but also introduce additional challenges for DBMSs due to their different characteristics compared to usual memory. One of them is additional data movements due to limited capacity or the higher latency of the underlying memory technology, requiring hybrid or adaptive approaches to compensate it effectively. Vast data movements reduce the overall performance of a DBMS since CPU resources are blocked until data transfer is completed. Unoptimized data locality in memory and storage, a known problem for GDBMS, further worsens the problem of data movements and hinders leveraging the full offered performance of underlying memory technology since it results in high random access. The Intel Data Streaming Accelerator, a CPU-integrated, DMA-based accelerator for memory operations, addresses this challenge by offloading data movement operations and freeing CPU resources. Unlike usual DMA engines, it offers a controllable interface to organize and offload memory movements. In this work, we leverage the memory operation accelerator, first to maintain data locality in a graph DBMS (GDBMS) effectively using an LSM-based memory layout approach, and second to provide a hybrid DRAM-HBM solution to accommodate both transactional and analytical workloads.