Implementation of efficient multipliers using stacker based binary compressors
P. Bhargavi, Pamanji Silpa, R. Sai Bhargav, Shaik Alisha, Ganekanti Naresh · 2025
Efficient multiplier design is essential for enhancing the performance of digital systems, particularly in applications that require rapid arithmetic processing. This study presents a multiplier architecture based on the Vedic Urdhva Tiryagbhyam method, integrated with approximate compressors for partial product accumulation using 5:3, 6:3, and 7:3 configurations. The proposed design is compared with conventional architecture that employs stacker-based binary compressors. Both implementations are synthesized and analyzed using the Xilinx Vivado environment, focusing on key performance indicators such as lookup table (LUT) utilization, static power, and dynamic power consumption. The simulation results demonstrate notable improvements in the proposed method. LUT usage is reduced from 596 to 56, static power consumption decreases from 0.823 W to 0.136 W, and dynamic power consumption drops from 48.008 W to 15.363 W. These outcomes highlight the proposed architecture’s advantages in terms of area efficiency and power reduction. The integration of approximate compressors with the Vedic multiplication technique proves to be a promising solution for designing compact, energy-efficient, and high-performance digital arithmetic units.