A Configurable Parallel Architecture for Singular Value Decomposition of Correlation Matrices
Luis Edwin López López, David Luviano Cruz, Juan Cota-Ruiz, José Díaz, Ernesto Sifuentes, Jesús Silva-Aceves, Francisco Enríquez-Aguilera · Electronics · 2025
Singular value decomposition (SVD) plays a critical role in signal processing, image analysis, and particularly in MIMO channel estimation, where it enables spatial multiplexing and interference mitigation. This study presents a configurable parallel architecture for computing SVD on 4 × 4 and 8 × 8 correlation matrices using the Jacobi algorithm with Givens rotations, optimized via CORDIC. Exploiting algorithmic parallelism, the design achieves low-latency performance on a Virtex-5 FPGA, with processing times of 5.29 µs and 24.25 µs, respectively, while maintaining high precision and efficient resource usage. These results confirm the architecture’s suitability for real-time wireless systems with strict latency demands, such as those defined by the IEEE 802.11n standard.