FPGA-based softcore multiplier design based on look-up table encoding
Burhan Khurshid · Engineering Research Express · 2025
Abstract The indispensability of the multiplication operation in digital signal processing applications is well established. Most of the contemporary multiplier designs are mainly suited for ASICs. Implementing ASIC-based designs on FPGAs does not yield significant performance gains due to the fundamental architectural difference between the two platforms. Few FPGA-based multiplier designs have been proposed recently that focus on exploiting the architectural features of FPGAs, like LUTs and Carry4 primitives. However, these designs are far from optimal because the full computation potential of the underlying FPGA resources is not exploited. While many FPGA vendors also include high-performance hardwired and softcore multipliers, they are typically limited in number and suffer from high interconnect delays due to their fixed position in the FPGA fabric. To counter these issues, we present a softcore multiplier design that optimally exploits the underlying FPGA resources. Our implementation is based on the methodology that restructures the multiplier Boolean network so that the logic nodes are optimally distributed to LUTs and Carry4 primitives. While existing designs use Carry4 primitives only in the partial product reduction stage, our methodology enables the use of Carry4 primitives in both the partial product generation and partial product reduction stages. This results in reduced LUT count and a faster structure. Our 8-bit multiplier utilizes only 35 LUTs and has a PDAP of 2740 as against 51 LUTs and a PDAP of 4454 for the area-optimized Xilinx IP multiplier and 60 LUTs and a PDP of 4660 for the speed-optimized Xilinx IP multiplier. This accounts for 31% and 41% improvement in LUT count and 38% and 41% improvement in PDAP compared to the area and speed optimized Xilinx proprietary multipliers. Similarly, compared to the best 8-bit softcore multiplier in the literature, our design shows an improvement of 33% in PDAP. These performance trends are not one-off but persist as the word length of the multipliers increases beyond eight bits.