Design Obfuscation and Performance-Locking Solutions for Mixed-Signal, Analog and RF ICs
Priyanshu Mishra, Andrew Marshall, Yiorgos Makris · 2025
Analog/RF Integrated Circuits (ICs) are particularly prone to reverse engineering as they consist of a limited number of design topologies and possess low transistor counts in their design blocks. Despite their simple structure, however, they require significant time and resources due to their custom design nature and their sensitivity to minute parameter variation. In this chapter, we review the various design-level and layout-level solutions which have been proposed toward protecting analog/RF hardware Intellectual Property (IP) from reverse engineering and unauthorized use. A popular approach uses a key-based mechanism to unlock the biases of analog/RF ICs to obtain specification-compliant performance. Combinational locking and parameter biasing obfuscation utilize a digital key to configure an array of transistors in a current mirror block or the physical dimensions of the transistors, respectively, to hide the biasing conditions of the analog/RF IC. Similarly, tuning elements such as memristors or analog floating gate transistors (AFGTs) can be used in trimmable analog/RF ICs to lock the performances of the circuit. Along a different direction, modification of existing parameterized cells (P-cells) using either process variation or layout structures to create polymorphic devices and camouflage them with process P-cells can also improve security of Analog/RF ICs through the use of fake contacts. Similarly, polymorphic devices can also be created by leveraging process variations effects such as Well-Proximity Effect (WPE) or Length of Diffusion (LOD). Most existing approaches to locking Analog/RF ICs suffer from a limited key space and are prone to removal attacks due to the digital nature of the key. Therefore, implementation of analog solutions which are embedded in the analog/RF IC will not only increase the key space but will also improve resilience against removal attacks. Accordingly, this chapter will conclude with guidelines for effective implementation of such purely analog locking solutions.