FPGA Routing Optimization Based on Multi-Level MUX Architecture
Xizheng Li, Kaichuang Shi, Wai-Shing Luk, Hao Zhou, Lingli Wang · 2024
The routing architecture significantly impacts FPGA performance and area. Traditionally, routing resources are divided into connection blocks (CBs) and switch blocks (SBs) to implement interconnects based on high-fanin multiplexers (MUXes). The number of MUX levels is typically fixed in past studies, resulting in signals traversing a consistent number of MUXes within defined routing blocks. Although there is a lot of research focusing on the routing model, how MUXes implement these connections is less explored. In this paper, we propose a novel routing architecture based on multi-level MUXes, allowing for flexible driving relationships based on connections through various numbers of MUX levels. We define parameters to describe the multi-level MUX architecture, covering the number of MUX levels and the type and number of MUX fan-ins, and conduct experiments to investigate the effectiveness based on these parameters. In addition, we employ Bayesian Optimization (BO) for design space exploration based on the above parameters and wire distribution. The experimental result demonstrates that the optimized multi-level architecture achieves a 13.6 % reduction in critical path delay (CPD) with a 4.3 % overhead in total routing area compared to General Routing Block (GRB) architecture using VTR benchmarks. The multi-level MUX result also surpasses the BO searched result without the exploration of MUX arrangement, showing improvements of 6.9 % in CPD and 2.1 % in total routing area. Additionally, it shows 8.6 % and 5.0% improvement in CPD and routing area respectively than the versatile interconnection block (VIB) architecture.