An Area-Efficient Lookup-Table -Based eDRAM Digital CIM Macro for Neural Network Inference
Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu · IEEE Journal of Solid-State Circuits · 2025
Digital circuit is a promising approach to implement computing-in-memory (CIM) architecture for data-intensive applications, such as neural network inference. Previous digital CIM implementations have demonstrated higher throughput and robustness than the analog counterpart, benefiting from technology scaling and full-precision datapaths. However, the traditional digital CIM designs adopt a bulky adder tree as the computing circuit, limiting further improvements in area and energy efficiency. To address the above limitation, this work proposes a novel design methodology that combines the lookup-table (LUT) and high-density embedded dynamic RAM (eDRAM) cells. By storing precomputed weight summations in LUTs, the proposed approach reduces the first two stages of the adder tree. Additionally, the row-level parallelism of the CIM architecture is utilized to amortize the overheads of LUT weight encoding and eDRAM refreshing. The 28-nm prototype demonstrates a peak area efficiency of 16.2 TOPS/mm2and an energy efficiency of 49.5 TOPS/W, both for 8-bit operations. The proposed eDRAM macro achieves a 2.4 and 0.48 Mb/mm2density in memory and CIM mode, due to its balanced computing-storage ratio, enabling reconfigurability between computing cores and memory storage.