Design and Implementation of Reliable Fault-Tolerant Data Transmission Using Triple Modular Redundancy and CRC-Based Error Detection
Sai Vyshnavi Danda, Saurabh Kesari, Shashank Kumar Singh, N Dharmachari, Jayaraj U Kidav, M K Linga Murthy · 2025
Reliable data transmission is crucial in safety- critical domains such as aerospace, healthcare, and telecommunications. This paper proposes a fault-tolerant design combining Triple Modular Redundancy (TMR) and Cyclic Redundancy Check (CRC-16) to enhance error detection and correction. TMR replicates data across three independent modules, using majority voting to mitigate single-point failures, while CRC-16 provides efficient detection of single-bit and burst errors during transmission.The architecture, implemented using Verilog HDL, includes modules for CRC encoding, TMR redundancy, and real-time error detection. Simulation results validate the design’s resilience, demonstrating robust fault tolerance, low latency, and high throughput. The scalable and modular approach ensures adapt- ability for diverse applications, offering reliable communication in fault-prone environments.