A RISC-V Coprocessor for Seamless Integration of Stream-Based Accelerators
Rohan Krishna Vijayaraghavan, Ahmed Kamaleldin, Matthias Nickel, Diana Göhringer · 2025
The increasing computational intensity of modern applications such as deep learning or computer vision has called for a shift in the focus of research towards heterogeneous architectures with specialized accelerators integrated with a system of general-purpose computing cores. However, integrating such accelerators requires deep hardware expertise, posing significant challenges due to steep learning curves and long development times. This work provides a modular and extensible hardware platform to seamlessly integrate stream-based HLS/RTL accelerators with a RISC-V-based general-purpose core. The platform extends the RISC-V ISA by providing a set of custom instructions to control and manage multiple stream-based accelerators directly through the RISC-V core. The accelerators are hosted by a coprocessor unit tightly coupled to the RISC-V core through the open-source eXtension Interface. The proposed RISC-V-based coprocessor features a modular and flexible architecture which can be configured with user-defined custom stream-based accelerators. The implementation of this coprocessor on an AMD/Xilinx RFSoC 4x2 board shows a lightweight design, occupying less than 4% of the available LUTs, and an evaluation of the coprocessor architecture indicates that data-intensive applications using multiple hardware modules sequentially or in parallel benefit the most.