A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing Approaches
José Ferreira Costa, Filipe Parrado de Azevedo, Ricardo Martins · 2025
The incorporation of process, voltage and temperature (PVT) corner conditions into reinforcement-learning (RL)-based analog integrated circuit (IC) sizing remains a challenge, as there are only a few attempts reported in the literature that explore this computationally intensive task. Therefore, this work presents a comparative study of five different approaches for integrating PVT conditions within state-of-the-art RL-driven sizing methodologies. Each approach begins with the same conditions to ensure a fair comparison, and are evaluated within the same circuit topology, comparing agent steps, number of simulations, execution time and final sizing functional behavior. Results reveal the trade-offs of each approach, and the best performing one for this problem is highlighted and discussed to facilitate more research activities within this field.