An Efficient Wide-Voltage Processor With PVTA Tolerance, Voltage Droop Mitigation, and Runtime Ultrafine-Grained Frequency Adaptation
Zhenhao Li, Runze Yu, Xi Deng, Zhaoxu Wang, Haoming Zhang, Zhenglin Liu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
Traditional processors require substantial design margins to account for process, voltage, temperature, and aging (PVTA) variations, resulting in significant energy efficiency losses. Existing dynamic timing error detection and correction (EDaC) techniques reduce these margins but incur high area overhead and design complexity. In this brief, we propose a processor based on the RI5CY core that integrates a PVTA tolerance and voltage droop mitigation adaptive voltage frequency scaling (AVFS) system. This approach reduces overhead to only 0.065%, enables ultrafine-grained frequency adaptation, and actively mitigates abrupt voltage droops. Additionally, a novel baud rate adaptive UART (BRA-UART) module ensures robust communication across all frequencies. Our processor design achieves a 163% typical performance gain and a 37.7% power reduction in the logic circuitry at near-threshold voltage (NTV), substantially improving energy efficiency.