PIM-BEACON: A Benchmarking and Emulation Framework Supporting Adaptive CONfigurations in DRAM-Based Processing-in-Memory Systems
Inseong Hwang, Jihoon Jang, Chae Min Park, Hyun Kim · 2025
The growing demand for data storage and memory bandwidth in large-scale deep neural networks has exacerbated the data movement bottleneck in traditional von Neumann architectures. Processing-in-memory (PIM) technology addresses this challenge by integrating computation within memory, reducing data transfer overhead. Prior research has predominantly relied on in-house PIM simulators for evaluation. However, these simulators often exhibit limited versatility and slow evaluation runtimes, constraining their effectiveness for comprehensive design space exploration. We present PIM-BEACON, a highspeed trace-based PIM emulation platform that ensures high reliability, fidelity, and versatility to address these limitations. PIM-BEACON adopts a modular design by configuring the PIM controller and emulator regions separately and employs SystemVerilog for FPGA-based high-fidelity implementation. To improve evaluation runtime, we introduce an efficient BRAM management mechanism that maximizes FPGA resource utilization. Supporting a wide range of DRAM-based PIM architectures, PIM-BEACON achieves up to 133.61 × faster runtime with only a 1.57 % average performance cycle error rate.