A novel modification and hardware implementation of the simplified AES algorithm for IoT applications
Vadapati Satya Sai Pavan Nishith, Adriza Saha, Ashish Patwari · Results in Engineering · 2025
• Modified S-AES: Introduces a novel modification to the Simplified AES (S-AES) algorithm, utilizing Boolean logic for the substitution box (S-box), six rounds of encryption, and interleaved Caesar cipher and shift-and-pad modules to reduce complexity while maintaining security. • ASIC Design: The modified S-AES algorithm has been implemented as an application specific integrated circuit (ASIC) design, using modern electronic design automation (EDA) tools. It was found to have lower area and power requirements compared to the original S-AES algorithm. • LightWeight Cryptography: The proposed algorithm has been designed for resource-constrained IoT devices, providing a cryptographic solution that fits within the strict power and hardware limitations typical of IoT edge devices. • Security Validation: The algorithm’s cryptographic strength has been analyzed using the Avalanche Effect model, and it was found to be satisfactory. With the rise of resource-constrained technologies like the Internet of Things (IoT) and Device-to-Device (D2D) communication, there is a growing need for lightweight yet strong cryptographic algorithms. This study aims to propose a modification to the existing simplified AES (S-AES) algorithm to better suit the lightweight cryptographic demands of IoT devices, while also implementing it as an Application Specific Integrated Circuit (ASIC) to evaluate its efficiency in terms of area and power consumption. The proposed modifications include: (i) replacing multiplexers with Boolean logic for the S-box, (ii) increasing the number of encryption rounds from two to six, and (iii) integrating an interleaved Caesar cipher and shift-and-pad module in each round. These changes significantly reduce the algorithm's complexity without compromising security. Physical design of both S-AES and MS-AES (proposed) was carried out using modern electronic design automation (EDA) tools as per the ASIC design cycle and it was found that the MS-AES needs at least 50% fewer hardware resources (area and power) than the S-AES. Additionally, a security analysis using the Avalanche effect model confirms that the encryption strength remains robust. The proposed framework provides a viable solution for on-chip hardware acceleration in IoT edge devices, offering a balance between low resource usage and strong cryptographic security.