EVA: A 16mm2 1.54TFLOPS Tiled-Based Accelerator for Evolvable Edge Computing
Junkang Zhu, Minsik Kim, Cheng‐Hsun Lu, Wei Tang, Tianyu Wei, Zhengya Zhang · 2025
EVA is an accelerator designed for evolvable edge computing applications. It integrates programmable processing array tiles (A-Tiles) for performance and utilization, and RISC-V CPU tiles (C-Tiles) for control and quick reconfiguration at a 100ns timescale. EVA features a versatile interconnect fabric, a distributed memory system, and flexible mapping. A 16mm2EVA test chip achieves a throughput of 1.54TFLOPS (FP16) at 0.9V and a peak energy efficiency of 708GFLOPS/W at 0.49V, demonstrating high compute density and efficiency for diverse workloads.