A High-Order Masking with Load-Delay-Equalized WDDL for Provable Side-Channel Security
Noriyuki Miura, Kazuki Monta, Takuya Wadatsumi, Jun Shiomi, Yukihito Hiraga, Takeshi Sugawara, Makoto Nagata · 2025
A custom WDDL is proposed for provably secure high-order masking. XOR/AND used in WDDL are designed by symmetric Pass Transistor Logic (PTL) to suppress data dependency in power/delay. A self-retimer is introduced to avoid accumulation of inter-stage power/delay variations due to unbalanced layout and routings. Those custom circuit techniques reduce data-dependent information leakage and non-ideal leakage due to unwanted coupling through supply and ground for proven high-order side-channel security.