m-Zephyr: A Digital In-Memory Ising Chip with 240 Spins Featuring Enhanced Connectivity Based on a Modified 3D Zephyr Topology
Yihao Wu, Jooyoung Bae, Chaeyun Shim, Bongjin Kim · 2025
We present a digital in-memory Ising computing chip with a modified 3D Zephyr topology implemented using a 65nm CMOS technology. This design features cross-dimensional connectivity with 24 interactions per spin for the efficient mapping of complex combinatorial optimization problems to the Ising hardware. The proposed Ising chip with enhanced spin connectivity outperforms prior works in terms of reconfigurability, allowing the Ising chip to solve more difficult problems with complicated topologies and higher dimensions, but minimizing hardware mapping overhead.$24\times 7$-bit precision coefficients are stored in memory and used to compute spin interactions, minimizing energy consumption and computing latency while ensuring accuracy with fully digital and high precision computing. Measured results show$> 100\times$speedup than the baseline algorithm while finding better optimal solutions with lower Mean Ising Hamiltonian values.