A 3nm 125 Tops/W-29 TFLOPS/W, 90 TOPS/mm2-17 TFLOPS/mm2 SRAM-Based INT8 and FP16 Digital-CIM Compiler with Multi-Weight Update/Cycle
Haruki Mori, J-M. Hung, Weisheng Zhao, Kavita Khare, Brian Crafton, H. Ishii, C.H. Lee, X. Peng, Xiaoyu Sun, Y. Fujino, Charles Tsen, Vinay Joshi, Chin-Lung Chuang, T. Hashizume, C-F. Lee, T.-J. Chou, Kerem Akarvardar, Saman Adham, Yih Wang, H. Fujiwara · 2025
This paper presents a DCIM compiler supporting INT8 and FP16 formats, offering configuration flexibility, high accuracy, and high area/power efficiency. Our 3nm test chip is fully validated and exhibits 124.6 TOPS/W at 0.5V and 90.2 TOPS/$\text{mm}^{2}$at 1.1 V for INT8 DCIM, and 28.6 TFLOPS/W at 0.5V and 17.4 TFLOPS$/ \text{mm}^{2}$at 1.1V for FP16 DCIM, respectively.