BiFrost: A Composable, Resilient Interconnect Network Architecture for Scalable Artificial Intelligence Systems
Gurpreet Singh Kalsi, Hong Wang, Jason Howard, Joshua B Fryman, Fabrizio Petrini, D. Klowden, Sanjaya Tayal, Anil Rao, Steve Pawlowski · IEEE Micro · 2025
Large Language Models demand extreme memory bandwidth and compute density, surpassing traditional architectures. Chiplet-based designs and 3D memory stacking offer solutions, but introduce challenges in integration, yield, and software compatibility. We present BiFrost, a composable network architecture that addresses these challenges through three innovations. BiFrost implements a FatTree network on chiplets, enabling intra- and inter-chiplet communication with 820 TB/s aggregate raw bandwidth and sub-100 ns latency in a 24 chiplet setup. A unified address space, enabled by a novel packet address compute unit, ensures compatibility with POSIX shared-memory models. Resilience is achieved through adaptive routing and dynamic memory remapping, ensuring graceful degradation upon faults. Built on a 3nm process, BiFrost features 0.48 mm2per 16 × 16 router and 17.2 mm2per chiplet. Flexible routing supports topologies like Dragonfly and HyperX. BiFrost maintains 90% peak bandwidth under uniform random traffic and offers OS-level configurability, enabling seamless scaling from single chiplet to multi-rack systems.