A Programmable Resolution Digital-to-Frequency or Period Converter With Sawtooth-Based Jitter Reduction
Nimit Jain, Eric A.M. Klumperink, Harm van Rumpt, Bram Nauta · IEEE Journal of Solid-State Circuits · 2025
Open-loop fractional output dividers (FODs) are compact, digital-intensive frequency synthesizers with instantaneous frequency switching capability. Traditional FODs linearly map a digital code to frequency [digital-to-frequency converter (DFC)] or to period [digital-to-period converter (DPC)] with a fixed frequency or period resolution, respectively. This article proposes a flexible FOD that can be reconfigured to a DFC or a DPC with a programmable frequency or period step size. An analog-sawtooth-based phase interpolation approach is used to cancel the digital quantization errors. The interpolation circuit exploits a dual-alternating slope digital-to-time converter (DTC) architecture with a delay that is insensitive to process, voltage, and temperature variations and is tolerant to power supply noise. Fabricated in GlobalFoundries 22-nm FDSOI technology, the proposed FOD prototype produces the output frequencies ranging from 132 to 404 MHz using a 3 GHz input clock while consuming 5.5 mW and occupying an active area of 0.032 mm2. The fractional spurs are below −50 dBc at the nominal condition and below −47 dBc across supply, bias current, and temperature variations after performing a one-time calibration at 0.9 V supply voltage and room temperature.