A data caching and distribution system for radar signals
Ping Zhang, Dabo Dong, X Mu, Hongxue Yang, Hui Du · 2025
This paper proposes an FPGA-based highperformance data caching architecture to address signal processing fluctuations in radar systems operating in complex electromagnetic environments. The solution incorporates reconfigurable GTH interfaces supporting dynamic rate adaptation from 2.5 to 5 Gbps, implements a dual-mode switching mechanism with sub-10 μ s transition capability, and enables seamless switching between DEBUG and normal operational modes. The architecture achieves 81.92 Gbps memory bandwidth at 200 MHz operation frequency, demonstrating a 20% throughput improvement over conventional approaches while maintaining data loss rates below 0.01% during operational mode transitions. These technological advancements provide a robust solution for reliable, low-latency signal processing in modern radar applications, particularly in challenging electromagnetic conditions. The system's performance enhancements and operational reliability have been experimentally validated, confirming its practical engineering value for advanced radar systems requiring stable processing capabilities during dynamic mode switching scenarios.