Weak PUF-Based Variable Latency Obfuscation Technique for ML-Attack Resilient Arbiter PUFs
Aranya Gupta, Bishnu Prasad Das, Sanjeev Kumar Manhas, Rajat Sadhukhan · IEEE Embedded Systems Letters · 2025
The conventional linear feedback shift register (LFSR)–based arbiter PUF (APUF) suffers from machine learning (ML) attacks, which is a challenge for employment in real-world authentication scenarios. To mitigate this vulnerability, our paper presents a weak PUF-assisted and challenge-dependent dynamic and non-linear feedback shift register (DNLFSR)-based APUF. The proposed technique introduces dynamic and variable iteration-based LFSR to make the generated challenge-response pair (CRP) space more non-linear, which effectively prevents attackers from modeling the APUF. The proposed DNLFSR-based APUF achieves ≈ 50% prediction accuracy (similar to random guessing) against various ML attacks carried out through exhaustive testing over 1 million CRPs. Additionally, the proposed technique reduces latency by ≈n/2 clock cycles for an n-stage LFSR compared to state-of-the-art techniques. Extensive performance evaluation of the proposed DNLFSR-based APUF on both Python simulation and FPGA hardware implementation shows near-ideal uniformity, uniqueness, and reliability for 64-bit and 128-bit DNLFSR-based APUF. Moreover, the proposed design consumes low hardware overhead, showing a minimum 43.2% reduction in LUT usage compared to the state-of-the-art techniques, making it a lightweight solution for IoT applications.