A Novel Area Efficient and High‐Speed BCD Adder Using CFA and Multiplexer in Quantum‐Dot Cellular Automata
Nagarjuna Telagam, D. Ajitha, S. M. Prabin, Boppidi Srikanth, Nehru Kandasamy · IEEJ Transactions on Electrical and Electronic Engineering · 2025
This paper proposes a new enhanced Single Digit BCD Adder (SDBA) to perform decimal addition optimally. Quantum‐dot Cellular Automata (QCA) will construct nanostructured arithmetic circuits for future computing. One of the vital structures in arithmetic structures is the Binary Coded Decimal (BCD)/Decimal Adder. The existing Decimal Adders require many cells and consume more delay, which makes the circuit inefficient in doing decimal addition faster. The binary adder structures are more significant in deciding the performance of conventional BCD adders. Multiplexers are used in the proposed BCD adder to enhance the speed with less complexity. The main contribution of the proposed SDBA design is to replace the final part of the conventional structure Carry Flow Adder (CFA) based BCD adder with a multiplexer, which improves the speed and increases the regularity of the structure. The multiplexers perform the binary to decimal sum conversion in parallel rather than the carry rippling in the lower part of the standard circuit. The SDBA uses the optimized CFA Type‐II binary adder and new logic with a 2:1 multiplexer. Furthermore, the proposed BCD adder is an optimized design in terms of delay, which requires 2.75 clock cycles only compared to the recent designs. © 2025 The Author(s). IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.