A Serial–Parallel Mixing-Mode Matrix–Vector Multiplication Architecture for Large-Scale In-Storage Computing With Ultrahigh Parallelism in nand Flash Memories
Yu-Yu Lin, Feng-Ming Lee, Pei-Ying Penny Du, Chih-Chieh Lin, Chih-Chang Hsieh, Ming-Hsiu Lee · IEEE Transactions on Electron Devices · 2025
A novel mixing-mode in-storage-computing (iSC) architecture is proposed and derived as an efficient and promising approach for large-scale matrix– vector multiplication (MVM) operation. It was demonstrated through both 2-D CMOS-compatible SONOS NAND flash and 96-layers 3-D NAND flash memories. The sum-of-product (SoP) results are achieved by summing the input-weight products from all the series-connected cells in each NAND string and then combining the results from multiple blocks on the same bitline. Multiple NAND cells and multiple resistance states per cell can be utilized to represent multilevel weight values. Two approaches are proposed to eliminate the architecture-induced variation through analyzing the steady-state equivalent resistance. High MVM computing capabilities with typical memory chip power consumption are achieved, which exploit the potential of NAND flash devices in executing large-scale neural network models.