Design and Implementation of High-Performance RISC-V Processor with Five Stage Pipeline on FPGA
B. V. V. Satyanarayana, Nangedla Madhu, K. Srinivas · 2025
The rising need for high-performance yet energy-efficient computing in embedded and portable systems has led to the advancement of low-power processor architectures. This paper introduces the design and implementation of a RISC-V processor featuring a five-stage pipelined architecture, developed using Verilog Hardware Description Language (HDL). The proposed design emphasizes performance optimization while ensuring minimal power consumption, making it suitable for constrained computing environments. Leveraging the advantages of the Reduced Instruction Set Computer (RISC) architecture—such as simplified instruction sets, reduced complexity, and uniform instruction execution the proposed processor is optimized to enhance instruction throughput while minimizing latency. The design integrates essential components including the Arithmetic Logic Unit (ALU), decoders, memory units, register file, multiplexers, and pipeline registers (IF/ID, ID/EX, EX/MEM, MEM/WB), along with a hazard detection unit to efficiently resolve data and control hazards. Furthermore, the processor supports RISC-V extensions such as floating-point arithmetic, bit manipulation, vector operations, and cryptographic functions to broaden its computational capabilities. Cache memory architecture is also explored, emphasizing its impact on access latency, bandwidth, and overall system performance through effective memory hierarchy strategies.