Power, Performance and Area Analysis of Real-Valued FFT Architectures
B. V. V. Satyanarayana, K. Kiran, K. Mohana Pranitha, P. Chinnu, M. Mounika Devi, K. Pranay · 2025
Fast Fourier Transform (FFT) is a prominent digital signal processing algorithm with extensive applications in frequency domain analysis. Its computational complexity requires a large amount of hardware resources, thus resulting in high power consumption. This project proposes an efficient FFT architecture that targets real-valued signal processing optimized with Vivado to achieve the goal of low power, high performance, and minimal hardware complexity. The design proposes two methods: the Input Grouping Method and the Partial Sum Sharing Approach. The Input Grouping Method reduces multiplications by rearranging input values with the same twiddle factors, minimizing computational overhead. The Partial Sum Sharing Approach improves efficiency by recycling intermediate sums, reducing the number of adders and complexity. These advancements enhance power efficiency, area usage, and computation delay over conventional FFT designs. A key component is a pipelined radix-16 Booth multiplier, optimized for low power and reduced complexity. The parameters are set up based on 32-bit input data and produce efficient 8-bit outputs with 32-bit and 64-bit input configurations. Moreover, the FFT multiplier utilizes an advanced adder structure to reduce delay and power consumption. Based on these optimizations, system performance is dramatically improved with a 32-point FFT architecture implementation. Simulations and synthesis is done in Vivado and validate reductions in power dissipation, area consumption, and computation latency is obtained. Scalability in the architecture lends itself to use in real-time applications for digital signal processing and embedded systems. In-depth examination of performance characteristics indicates its supremacy over traditional FFT designs. Such techniques effectively mitigate hardware efficiency problems, making it a viable option for resource-constrained environments. By applying sophisticated optimization techniques, FFT implementations can be made much more efficient, enabling highly effective digital signal processing solutions.