Hybrid Approximate Multipliers With Merits Balance for Digital Processing and Neural Networks
Weiwei Shi, Xiaocong Cao, Zhuoliang Zou, Yuping Gao, Jiasheng Wu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
In this article, hybrid approximate multiplier (HAMs) designs based on the combination of logarithmic multiplication and piecewise linear (PWL) fitting are proposed. After extracting the exponent and mantissa of the input operands, two new variables are introduced to perform spatial mixed linear fitting on the 3-D surface of the mantissa product in different regions. Limited power-of-2 elements in line slopes make the multivariable mixed PWL computational simple and friendly to logic circuit complexity. With iterative adjustment of the slopes and bias of the lines in the PWL calculation, the relative error distance (RED) distribution is well balanced and zero concentrated. In addition, we detail the logic architecture to implement approximate hybrid accumulation and error-tolerant complement conversions. In the 45-nm library-based performance comparison, the proposed multipliers—mainly 16-, 8-, and 32-bit floating-point multipliers—exhibit >55% power, >23% delay, and >43% area reductions compared with the exact multiplier. In addition, they outperform other state-of-the-art designs in terms of delay, power, area, and error, as evaluated by the joint delay–power–area product (PPA) and mean RED (MRED). In case experiments, the proposed multipliers perform nearly equivalently to the exact multiplier in error-tolerant digital processing and neural network computations.