Single-Layer Parity Generator and Checker Design Using XOR Gate in Quantum-Dot Cellular Automata (QCA)
Rohit Kumar Shaw, Angshuman Khan · 2025
Quantum-dot cellular automata (QCA) offer a high-performance, low-power alternative to traditional VLSI technology for nanocomputing. However, the existing metal-dot QCA-based parity generators and checker circuits suffer from increased energy dissipation, larger area consumption, and complex multilayered layouts, limiting their practical feasibility. This work designs a 3-bit parity generator and 4-bit checker to address these challenges using an optimized modified majority voter-based Ex-OR gate in QCA. A single-layered layout was simulated in QCADesigner 2.0.3, avoiding crossovers to reduce fabrication complexity. Energy analysis using QCADesigner-E reveals 34.4 meV energy consumption, achieving 31% energy efficiency and 75% area efficiency in the context of QCA costs compared to recent designs. The proposed circuit highlights the unique potential of QCA as a scalable, energy-efficient solution for high-density next-generation computing systems.