Massive QoS-Aware Packet Queueing and Traffic Shaping at the Access Edge Using FPGAs
Ralf Kundel, Lisa Wernet, Fridolin Siegmund, Leonhard Nobach, Hans‐Joerg Kolbe, Tobias Meuser · 2025
Large-scale packet queueing and scheduling is the basis for today's Quality of Service (QoS) in computer access networks, especially to achieve guaranteed high throughput and low latency. The throughput of a single network function, implementing the QoS functionality for a large number of customers, is in the range of hundreds of gigabits or even more. Therefore, a good performance of the underlying hardware is mandatory. While highly-performant fixed-function ASICs offer sufficient functionality for most data center use cases, as of today, they cannot support all functionality required for access networks, including QoS-aware packet queuing. In this paper, we first analyze mobile and residential Internet access requirements from an Internet service provider perspective, focusing on the QoS-aware packet queueing needs. Considering this analysis, we present a universal and generic FPGA design for high-performance packet queueing and scheduling. Our evaluation results show that FPGAs can be used to implement a deterministic QoS packet queueing system with high performance. This concept can extend today's programmable networking ASICs with the desired functionality as an offloaded “sidecar”.