Execute Your Darlings: Dynamic Execution of High-Level Formal Specifications for Validation and Early Prototyping
Robert Kunzelmann, Zeyad Tahoun, Wolfgang Ecker · 2025
The increasing complexity of modern hardware designs necessitates shifting from traditional Register-Transfer Level (RTL) abstractions to higher-level modeling approaches.One of these approaches, the Universal Specification Format (USF), based on metamodeling and embedded in the Python programming language, enables the uniform expression of digital hardware systems' functional and temporal behavior.While USF models are inherently static, conventional hardware development heavily relies on simulation for tasks ranging from early validation and debugging to dynamic verification and virtual prototyping.Bridging the gap between static specifications and dynamic development needs, we present a novel code generation approach that transforms USF models into executable behavioral models.Our method employs static scheduling with user-defined parallelism, producing executable and synthesizable models for cycle-accurate hardware simulation and emulation.Applying our approach to both the simulation and synthesis of a concrete component specification and variants hereof demonstrates the feasibility and reusability of the proposed code generator.