Power, Performance, and Area Analysis of Ultra-Stacked Forksheet-FET for Angstrom Nodes
Junjong Lee, Sanguk Lee, Yonghwan Ahn, Minchan Kim, Gunryeol Cho, Sunmin Yeou, Sung Kyu Lim, Rock‐Hyun Baek · IEEE Transactions on Electron Devices · 2025
For the first time, this study investigated the standard cell and chip-level power, performance, and area (PPA) benefit of ultra-stacked forksheet-FET (FSFET) with five channels for Angstrom nodes. Five-stack FSFET shows a smaller channel width than conventional four-stack FSFET at the same drive current condition, enabling additional scaling. In conventional nanosheet-FET (NSFET), a large number of channels increases parasitic resistance and capacitance, which degrades device performance. However, the wall of FSFET, the wrap-around contact, the metal source/drain, and the small vertical spacing of the channel can mitigate the increases in parasitics. Therefore, a five-stack FSFET can achieve a small footprint without frequency degradation. We developed 4T standard cells with heights of 76 and 68 nm for four-stack FSFET and five-stack FSFET, respectively. In the same device performance condition, the five-stack FSFET-based cells show a smaller energy-delay product due to the small capacitance. Five-stack FSFET-based chip shows a 10.5%~10.7% smaller area and 7.0%~7.5% shorter wire length for all benchmarks. The shorter wire length reduces wire capacitance; thus, the five-stack FSFET-based chip shows a smaller power consumption. On the other hand, the five-stack FSFET has a smaller metal width and a larger wire resistance. However, the five-stack FSFET-based chip shows only a slight increase in power-delay product (PDP) due to the gate-dominated circuit, great optimization using buffer insertion, and a backside power delivery network (BS-PDN). Overall, the five-stack FSFET-based chip shows only a slightly degraded PDP with 10.5%~10.7% smaller area. Ultra-stacked FSFET enables additional scaling, with only an increase in channel number before adopting complementary-FET (CFET).