Architectural Design Exploration of a Lane Detection Vision Pipeline for FPGA-based F1Tenth Autonomous Vehicles
Andrea Magnani, Gianluca Brilli, Andrea Marongiu · 2025
Heterogeneous System on Chip (HeSoC) based on reconfigurable accelerators, such as Field-Programmable Gate Arrays (FPGAs), offer a promising solution to meet the performance and energy efficiency demands of advanced perception and localization tasks in autonomous vehicles.This study investigates the hardware acceleration of a computer vision pipeline for lane detection on an FPGA, specifically targeting the AMD Kria KV260 device.We evaluate various integration architectures, memory organizations, and offloading strategies for integrating the multiple components of the pipeline.Experimental results demonstrate that the proposed solutions achieve up to 22× speedup compared to a software-only implementation, highlighting significant improvements in resource usage and processing efficiency.