FPGA-BASED ANALYSIS AND PERFORMANCE EVALUATION OF FIR FILTERS
D.S. Vidhya, Ishan Prabhu, Sohan Sawant, Melba D’souza, Sagar Shetkar · ShodhKosh Journal of Visual and Performing Arts · 2024
Finite impulse response (FIR) filters are widely used in digital signal processing because of their many benefits. Because these filters are naturally stable, stability issues during design and implementation are resolved. FIR filters have historically been made using ASICs or DSP processors. On the other hand, the incorporation of specialized DSP blocks and fundamental characteristics like re-configurability, reusability, cost effectiveness, and scalability have made FPGAs a preferred platform for the implementation and testing of digital signal processing systems. Optimized convolution algorithms can effectively realize FIR filters, even though they usually require a high order. The main goal of this project is to implement the FIR filter design on an FPGA. Traditional FIR filter design methods often have limitations in terms of processing delay, memory usage, power consumption, and overall system performance. To address these problems, this project uses the Distributed Arithmetic with Offset Binary Coding (DA-OBC) technique. By enabling high-speed operation and lowering hardware resource consumption, this technique improves performance while minimizing circuit complexity. Verilog HDL was used to design the FIR filter, which was then implemented using the Xilinx ISE Design Suite 14.7. MATLAB was used to generate the filter coefficients, allowing for accurate and effective filter design.