Optimized 64-Bit Carry Select Adder Using Enhanced Full Adder for Reduced Power and Delay
Sankara Rao Allada, Anjanee Kumar, Kandregula Jyoshna, Kirla Pravallika, B. Medisetti Chandrasekhar, Konathala Venkat · 2025
We aim to design an approximate 64-bit Carry Select Adder (CSA) by enhancing the full adder using a Look-Up Table (LUT) structure.In today's digital world, where nearly everything relies on digital chips, electronic adders play a crucial role in performing arithmetic operations within these systems.Although many techniques already exist, we propose a novel method for constructing a CSA.Our approach utilizes an improved full adder design incorporating multiplexers (MUX) to minimize power consumption, area usage, and propagation delay.