Wallace Tree Multiplier Using Reversible Logic With Brent-Kung Adder
Ajithkumar P.R, I Gokulakrishnan, Senthamizh Selvi R · 2025
The design and implementation of a Brent-Kung adder using reversible logic to produce a high-speed signed Wallace Tree Multiplier. The Wallace Tree Multiplier is well- known because of its tree-like structure and success in minimizing multiplication delay. Our approach utilizes reversible logic to improve power efficiency by limiting energy dissipation and preserving input information. Furthermore, the Brent-Kung adder improves carry propagation, which speeds up computation overall. According to experimental data, the suggested multiplier is appropriate for high-performance computing applications since it delivers lower delay and power consumption compared to standard architectures that use parallel adders and Kogge-Stone adders. The proposed Wallace tree multiplier using reverse logic with Brent Kung adder is designed and simulated on AMD Vivado 2023.2 and the overall on-chip power was 8.133 W, which is 76% less than traditional architectures, and the critical route time delay was 10.767 ns, which is 51% less than traditional wallace tree multipliers. The suggested architecture outperforms the Kogge-Stone adder integrated architecture by 45% respectively.