Hardware Accelerated Deep Learning for Real-Time Handwritten Signature Verification
Siri Dhari Kataru, R V Rohith, Deepak Sharda, S. Malarvizhi · 2025
Signature forgery detection is paramount for ensuring authentication integrity across security critical domains. This paper presents a multifaceted investigation into three heterogeneous deep convolutional neural network (CNN) architectures namely, a Siamese network, a fine-tuned VGG-16 model, and a quantized custom CNN applied to the CEDAR dataset for binary classification of genuine versus forged signatures. While software implementations exhibit robust discriminative capabilities, hardware acceleration via HLS4ML targets real-time inference on FPGAs. The Siamese network’s dynamic input pairing posed challenges for synthesis due to toolchain limitations, while VGG-16’s extensive parameter footprint led to resource exhaustion, preventing successful deployment. Conversely, the custom CNN, quantized to 6-bit fixed-point, achieved successful RTL synthesis on the PYNQ-Z2 (Zynq-7000) FPGA. This work elucidates trade-offs between computational complexity, classification performance, and hardware deployability, with future enhancements proposed for bitstream synthesis and model optimization.