Instruction Level Parallelism Optimizations in a High-Performance Dual-Issue RISC-V Processor for Real-Time Control Systems
Qingchen Zhai, Weiying Wang, Yueyue Wang, Yuanyang Xiang, Xu Chen, Kunyu Zong, Ruozhou Xiao, Zhiwei Zhang · 2025
This paper presents optimization efforts on instruction-level parallelism in D-RTCore, a seven-stage dual-issue RISC-V processor designed for real-time control applications. To enhance instruction fetch and dispatch efficiency, we introduce four key techniques: branch prediction optimization, variable-length hardware loops, dynamic instruction fusion, and out-of-order write-back without a reorder buffer (ROB). Performance evaluations reveal that D-RTCore achieves cycle reductions of up to 79% compared to the industry-standard TI C28x. For example, it executes the complex fast fourier transform with a 44% reduction in cycles and the fast fourier transform magnitude with a remarkable 79% decrease in cycles. These results highlight D-RTCore’s advanced execution capabilities, making it a competitive solution for real-time control systems that require efficient processing.