A 1.91 POPS/W Energy-Efficient SRAM Based Signed Multi-Bit Time Domain CIM Architecture
Subhradip Chakraborty, Dinesh Kushwaha, Himanshu Ranjan, Sudeb Dasgupta · 2025
In this paper, we present an area and energy efficient multi-bit signed SRAM based time-domain compute-in-memory (TDCIM) architecture. We have proposed an area efficient time-domain multiplication bit-cell (TDMC) for signed/unsigned operation. The proposed TDMC is 1.5× times area efficient than state-of-the-art. The work uses a time domain computing approach that uses combination of delay and pulse width to represent the equivalent multiplication and accumulation (MAC) operation performed. The proposed TDCIM focuses on improving the energy efficiency of the MAC operation. A time to digital converter (TDC) is used instead of analog to digital converter (ADC) to save power and area consumption. It achieves 1.3× higher energy efficiency compared to state of the art. The designed architecture has been implemented using a 28 nm FDSOI STM technology, resulting in the development of an 8 Kb TDCIM macro. This work achieves a normalized energy efficiency of 1910.45 TOPS/W at VDDof 0.8 V. The architecture achieves an inference accuracy of 91.20% on the CIFAR-10 dataset with 8-bit precision in inputs and weights.