A New 16-Bit IoT ASIC Design for the AES Encryption Algorithm
Doaa Ashmawy, Arash Reyhani-Masoleh · 2025
Previous works to secure IoT devices have mainly focused on 8-bit hardware architectures for AES encryption. In this paper, we present a new 16-bit ASIC design for AES encryption optimized for IoT systems. Our design includes a new 16-bit key derivation circuit that generates keys dynamically in parallel with the datapath, enhancing security by avoiding key exposure and protecting against existing attacks. Our design employs column-wise byte ordering for both the datapath and key derivation, eliminating the need for external reordering and reducing hardware resource usage. Additionally, we design a lightweight 16-bit serial MixColumns circuit that supports higher data rates compared to existing designs. ASIC implementation results using a 65nm CMOS technology library demonstrate a 50% increase in throughput with a 21% increase in area over previous 8-bit based designs. Our lightweight and fast AES ASIC design offers a tailored solution for securing IoT systems.