CAMC: A Multi-Chiplet Accelerator With Heterogeneous Memory-Based Computing Architecture For DNN Training
Xiaobai Chen, Hao Dong, Jiacheng Mei, Jun Li, Yifei Tian, Jieming Yin, Fu Xiao · 2025
Deep Neural Networks (DNNs) are extensively utilized in various fields due to their remarkable performance. However, as DNN models increase in complexity and size, the training process incurs substantial data transfer costs between computation and storage. The slowdown of Moore’s Law further challenges the integration of additional resources on a single chip, making it difficult to improve storage capacity and reduce off-chip data transfers. To address these challenges, we propose CAMC, a multi-chiplet DNN accelerator with a heterogeneous memory computing architecture. CAMC integrates SRAM-based in-memory computing with TSV-stacked DRAM-based near-memory computing. In addition, an efficient mapping strategy was developed to optimize resource utilization and performance. The experimental results demonstrate that CAMC enhances energy efficiency by 11.84 times and reduces data transfer costs by 8.78 times compared to the baseline design.