SPIKA: 200-TOPS/W RRAM-based Neural Network Accelerator Chip
Khaled Humood, Patrick Foster, Shiwei Wang, Alexander Serb, Themis Prodromakis · 2025
The development of non-volatile Compute-In-Memory (nvCIM) technology has demonstrated significant potential in addressing the data movement and Multiply-and-Accumulate (MAC) bottlenecks in machine learning algorithms by enabling parallel analog Vector-Matrix Multiplication (VMM) operations directly within memory arrays. In this work, we introduce SPIKA, a fully integrated RRAM-CMOS chip designed for neural network acceleration. The key innovation of SPIKA lies in its ability to efficiently transfer input signals to output signals with minimal circuit overhead. The VMM operation is performed in the time domain, with the dot product accumulated on a switched capacitor, eliminating the need for high-resolution, power-intensive data converters. Implemented using commercially available 180nm technology, SPIKA operates on a 64×128 crossbar and utilizes 4-bit inputs, ternary weights, and 5-bit outputs. The chip is evaluated on the MNIST dataset, achieving a peak throughput of 1092 GOPS and an energy efficiency of 195 TOPS/W.