Machine Learning-Driven Fast Carry Look Ahead Adder Architecture Using Simple Carry Checker
M. Shunmugathammal, Ganti Sri Ramya, M. S. Roopa, S. Nagarajan, K. Lalitha, M. Shagar Banu · 2025
In VLSI design, adders and multipliers are vital in performing summing and multiplying operations in different ways. Advances in VLSI technology have led to the emergence of designer adders with increased efficiency and cost-efficiency. Carry Look Ahead Adder (CLA Adder) is used in various operations where the system must add many bits with at least three inputs. CLA Adder is mainly used because of its ability to predict the carry before actually summing the inputs, reducing the overall execution time of the entire process. Still, there can be errors when the carry has been predicted. This paper proposes a new algorithm called 'Simple Carry Checker' based on approximate computing, which is used to reduce the frequency of errors in CLA adder while generating the carry of the inputs with a reduced execution time.