Optimized Auxiliary Classifier Wasserstein Generative Adversarial Network espoused Hypergraph Partitioning for VLSI Circuit Design
R. Pavithra Guru · International Journal of Information Technology & Decision Making · 2025
Partitioning is a fundamental problem in computer science and plays a significant role in very large-scale integration (VLSI) circuit design. Effective partitioning significantly impacts design quality and efficiency, particularly in chip design workflows. Existing partitioning methods, such as machine-learning (ML) methods, have shown limitations in performance, necessitating the development of more effective solutions. This study aims to improve partitioning and floor planning in VLSI circuit design by proposing an optimized method that enhances partitioning accuracy, minimizes area usage and reduces delay. The Optimized Auxiliary Classifier Wasserstein Generative Adversarial Network espoused Hypergraph Partitioning for VLSI Circuit Design (HGP-ACWGAN-BEPOA) framework is proposed to generate hypergraph partitions for VLSI circuit design, ensuring improved floor planning. To enhance partitioning efficiency, the binary emperor penguin optimization algorithm (BEPOA) is applied, optimizing hypergraph partitioning for better design quality. The model is trained and evaluated using benchmark circuit datasets to assess its effectiveness. Experimental results demonstrate that HGP-ACWGAN-BEPOA achieves superior performance compared to the existing models. It reduces area usage by 20.19%, 15.61%, and 18.27%, decreases delay by 22.78%, 20.67%, and 15.98%, and lowers power consumption by 25.79%, 20.19%, and 30.12% when compared to the existing models, such as OPFP-WO-ABSO-VLSI, SSGNN-GPP-VLSI, and AP-VDUG-VLSI, respectively. The proposed HGP-ACWGAN-BEPOA framework effectively enhances hypergraph partitioning for VLSI circuit design, improving efficiency in floor planning, reducing resource consumption and outperforming existing methodologies. This approach provides a promising direction for advancing partitioning techniques in VLSI circuits.