Rapid AI-driven Power-Thermal Intelligent DVFS for HPC Applications
Yang Zhi, Yong Pei, Mohamed M. Eldafrawy, Santosh Raghavan, Liming Gong, Igor Arsovski, Richard Ozaki, Junping He, Vivian Zheng · 2025
As artificial intelligence (AI) workloads scale, power consumption has become a major constraint in modern data centers, with AI servers alone projected to consume over 130 TWh annually by 2027. High-performance computing (HPC) applications face increasing thermal challenges due to rising power densities and shrinking silicon nodes, leading to performance degradation, energy inefficiencies, and reliability concerns. While Dynamic Voltage and Frequency Scaling (DVFS) is widely used to optimize power efficiency, existing strategies struggle to capture real-time power-temperature interactions accurately, limiting their effectiveness. Traditional Finite Element Analysis (FEA)-based thermal modeling is too computationally expensive for real world high-resolution transient simulations, making rapid power-thermal co-optimization infeasible. To address this challenge, we introduce an AI-driven power-thermal co-design framework based on Boundary-Condition-Independent Reduced-Order Modeling (BCI-ROM). This approach integrates experimentally calibrated FEA models with ROM-based predictive modeling, enabling real-time simulation of transient power-temperature dynamics with over 1000x speedup compared to conventional methods. Our methodology allows rapid design space exploration while maintaining the accuracy of traditional FEA, as validated by temperature deviation analysis across timescales from microseconds to 10 seconds, where a maximum deviation of only 0.3°C was observed. We further enhance this framework by incorporating an AI-enabled optimization strategy for DVFS control. Unlike conventional DVFS implementations that rely on static or coarse-grained heuristics, our approach dynamically adjusts frequency and voltage based on real-time temperature feedback, ensuring peak performance without exceeding thermal constraints. By tailoring power modulation strategies to different cooling capabilities, we eliminate unnecessary thermal margins, fully utilizing the chip's power envelope while maintaining safe operating conditions. Experimental results show that this AI-enabled DVFS optimization reduces workload completion time by over 20%, highlighting significant performance gains. Overall, this work presents a scalable, high-precision power-thermal co-optimization methodology that redefines DVFS strategies for AI and HPC applications. By enabling real-time power-temperature modeling and AI-driven decision-making, our approach enhances chip performance, optimizes energy efficiency, and ensures reliable thermal management, setting a new industry standard for next-generation semiconductor power optimization.