Leveraging Advanced Packaging for IP Protection in Heterogeneous AI Hardware
Md Saad Ul Haque, Jingbo Zhou, Farimah Farahmandi, Mark Mohammad Tehranipoor · 2025
The rapid demand for efficient AI hardware has driven the adoption of advanced packaging technologies such as 2.5D/3D integration. By enabling tight integration of CPUs, accelerators, and high-bandwidth memory (HBM) on a single silicon interposer, these technologies significantly boost performance, power efficiency, and memory bandwidth. However, this chiplet-based approach introduces new security challenges-most notably, increased risks of intellectual property (IP) piracy, reverse engineering (RE), and counterfeiting. This paper introduces a hierarchical co-obfuscation strategy that secures every layer of SiP-based AI hardware-from the package level down to the die level-fortifying both the interconnect network and compute chiplets. Our approach leverages hardware metering, locking mechanisms, split manufacturing, and sequential obfuscation to protect against both hardware- and software-based attacks, all while imposing minimal performance overhead (1%). The scheme further supports a keyless activation mechanism for hardware licensing, making it highly scalable for large high-performance computing (HPC) deployments.