WarmCache: Exploiting STT-RAM Cache for Low-Power Intermittent Systems
Noureldin Hassan, Byounguk Min, Changhee Jung, Yan Solihin, Jongouk Choi · 2025
This paper introduces WarmCache, an optimized STT-RAM cache design with relaxed non-volatility, for an energy harvesting system (EHS) to avoid such compulsory misses across power failure.The key insight is that if the retention time of a cache is longer than a power outage period, the cache contents can be preserved, thereby preventing compulsory misses.Based on this insight, WarmCache leverages a STT-RAM cache with reduced thermal stability to preserve non-volatility during power outages while not persisting any data.To mitigate retention failure that may occur in the relaxed STT-RAM cache, WarmCache lets its compiler partition program into a series of regions and conducts region-level error correction.At each region boundary, WarmCache verifies the execution of the region by scrubbing updated cache lines and re-executes it if any multi-bit error is detected therein.For optimization, WarmCache compiler introduces a novel region formation technique that adjusts the size of each region to match the scrubbing interval.This is achieved through region stitching for combining shorter regions and region splitting for dividing longer regions.Our experiments demonstrate that WarmCache manages to avoid compulsory cache misses and improves the performance by 1.3∼1.4x on average compared to the state-of-the-art cache design for EHS.