An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces
Dongwoo Kang, Jun-Soo Park, Y.-J. Kim, Sinho Lee, Kyugun Kim, Han-Gon Ko, Kwanseo Park · IEEE Transactions on Circuits and Systems I Regular Papers · 2025
This paper presents a single-ended three-level pulse amplitude modulation (PAM-3) transceiver employing crosstalk cancellation (XTC) techniques for next-generation memory interfaces. The proposed 3-ternery-to-4-ternery (3T4T) coding and feed-forward equalizer (FFE)-based XTC facilitate adopting PAM-3 signaling while maximizing channel density in the high-density memory interfaces. The proposed 3T4T coding reduces data-dependent jitter (DDJ) induced by inter-symbol interference (ISI) and mitigates the effect of crosstalk and maximum simultaneous noise (SSN) by half. The prototype transceiver is designed and fabricated in 28-nm CMOS process with a high-density on-chip channel which channel pitch is$1.0~\mu $m, obtaining an edge bandwidth density of 18 Tb/s/mm. The proposed PAM-3 transceiver achieves a crosstalk-induced jitter (CIJ) reduction of 0.846 unit interval (UI) with 90% CIJ reduction ratio at 18 Gb/s, and energy efficiencies of 1.103 pJ/bit and 0.764 pJ/bit for the transmitter and receiver, respectively. A bit error rate (BER) less than$10^{-12}$is verified with an eye margin of 0.40 UI.