Implementation of a Line Buffer in an Adaptive Gaussian Bilateral Filter
C. Saranya, P. Kumar, R Boomika, G S Harish · 2025
The proposed method presents the design and implementation of an FPGA-based filter architecture for image processing, focusing on the integration of a line buffer within an Adaptive Gaussian Bilateral Filter (AGBF). The AGBF aims to enhance edge preservation and noise reduction in real-time imaging applications. By leveraging FPGA platforms, the design achieves low-latency, high-throughput performance, essential for high-resolution image processing. The proposed architecture incorporates a line buffer to efficiently manage memory usage and facilitate seamless pixel-by-pixel processing, thereby reducing computational complexity and enhancing signal-to-noise ratio (SNR). Experimental results demonstrate the superiority of the proposed FPGA design in terms of power efficiency, processing speed, and image quality compared to traditional filtering approaches.